Coarse delay tuner circuits with edge suppressors in delay locked loops

ABSTRACT

The invention discloses a delay locked loop which includes a coarse delay tuner circuit with edge suppressors suitable for use with delay locked loops (DLLs). The disclosed tuner circuit provides reduced lock time of the DLL circuit.

The invention relates generally to a method and apparatus for a coarsedelay tuner circuit with edge suppressors suitable for use with delaylocked loops (DLLs).

A delay locked loop is an electronic circuit which can be used to matchthe internal clock of a synchronous integrated circuit device with anexternal clock, without error, i.e., to reduce so-called clock skew. Bycontrolling the time delay of the internal clock relative to theexternal clock, the internal clock can be synchronized with the externalclock. One important performance parameter of a delay locked loop is thelock time, or the time required for this synchronization to occur.

Accordingly, there exists a need for a delay tuner circuit which may beemployed in DLLs for reducing the lock time.

It is therefore a feature of the present invention to overcome the aboveshortcomings related to DLL lock time circuits by providing a method andapparatus for a coarse delay tuner which provides reduced lock times.Such DLL lock time circuits may be found in, inter alia, semiconductordevices which include a synchronous memory component, and apparatuscontaining such circuits.

In a first general aspect, the present invention presents a coarse delaytuner circuit for use with delay locked loops, said coarse delay tunercircuit comprising: an input node for receiving an input signal, whereinsaid input signal is a clock signal; a triggering circuit, saidtriggering circuit operationally coupled to said input node, whereinsaid triggering circuit is adapted to condition said input signal and toprovide a first output signal in response to a threshold level beingreached by said input signal; an edge suppressor circuit operationallycoupled to said triggering circuit, wherein said edge suppressor circuitis adapted to receive said first output signal, said edge suppressorcircuit adapted to provide a positive step signal as a second outputsignal, and wherein said edge suppressor circuit includes combinationalmeans for logically combining said first output signal and said secondoutput signal to produce a third output signal; and an output node foroutputting said third output signal.

In a second general aspect, the present invention presents a method forreducing lock time in a delay locked loop (DLL), said method comprising:providing an input node for receiving an input signal, wherein saidinput signal is a clock signal; providing a triggering circuit, saidtriggering circuit operationally coupled to said input node, whereinsaid triggering circuit is adapted to condition said input signal and toprovide a first output signal in response to a threshold level beingreached by said input signal; providing an edge suppressor circuitoperationally coupled to said triggering circuit, wherein said edgesuppressor circuit is adapted to receive said first output signal, saidedge suppressor circuit adapted to provide a positive step signal as asecond output signal, and wherein said edge suppressor circuit includescombinational means for logically combining said first output signal andsaid second output signal to produce a third output signal; andproviding an output node for outputting said third output signal.

In a third general aspect, the present invention presents asemiconductor device with a synchronous memory component, saidsemiconductor device comprising: a reference clock signal applied tosaid synchronous memory component; and a coarse delay tuner circuit forreducing lock time in said synchronous memory component.

In a fourth general aspect, the present invention presents a method ofproviding synchronization in a semiconductor device having a synchronousmemory device, said method comprising: providing a reference clocksignal applied to said synchronous memory device; and providing a coarsedelay tuner circuit for reducing lock time in said synchronous memorycomponent.

In a fifth general aspect, the present invention presents an apparatuscontaining a synchronous integrated circuit, said apparatus comprising:a synchronous memory component; a reference clock signal applied to saidsynchronous memory component; and a delay locked loop, wherein saiddelay locked loop includes edge suppressor means for reducing lock timein said synchronous memory component.

The foregoing and other features and advantages of the invention will beapparent from the following more particular description of embodimentsof the invention. It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary, butare not restrictive, of the invention.

The features and inventive aspects of the present invention will becomemore apparent upon reading the following detailed description, claimsand drawings, of which the following is a brief description.

FIG. 1 is a timing diagram representing a reference clock (REFCLK)signal and a corresponding coarse tuning circuit output signal inaccordance with an embodiment of the related art.

FIG. 2 is an electrical schematic diagram of a coarse delay tuner withan edge suppressor in accordance with an embodiment of the presentinvention.

FIG. 3 is a timing diagram representing the status of various signals atdifferent nodes of the circuit of FIG. 2 in accordance with anembodiment of the present invention.

The following is a detailed explanation of the structure and method fora coarse delay tuner circuit which may be employed in DLLs for reducingthe lock time, according to the present invention. It should be notedthat the same reference numbers are assigned to components havingapproximately the same functions and structural features in thefollowing explanation and the attached drawings to preclude thenecessity for repeated explanation thereof.

Many digital systems rely on accurate clocks to synchronize the timingof operations and data transfers. A crystal oscillator is often used togenerate a reference clock signal at some base frequency. This clocksignal is then divided or multiplied to create one or more clock signalswith desired frequencies. Alternatively, external clock signals can bereceived and likewise divided or multiplied to produce internal clocks.Delay locked loops (DLLs) and phase locked loops (PLLs) have becomemandatory in these synchronous integrated circuits (ICs) to preventclock skew, that is, the comparative difference between the phase andfrequency of a reference clock signal, when compared with the phase andfrequency of a feedback clock signal. When the difference between thephase and frequency is essentially zero, or within some specifiedtolerance, a “lock” is achieved. Minimizing the time required to achievethis DLL lock, i.e., the lock time, is an increasingly challengingproposition, particularly with DLLs in deep sub-micron integratedcircuit chips.

One way to ensure a lock, and to also have reduced lock time, is to usea coarse delay tuner circuit. A DLL without such a coarse delay tunercircuit results in the lock time of the DLL being relatively high, andsometimes the locking process gets tedious. A typical coarse delay tunercircuit operates by shifting the rising edge of the incoming clock pulseby a large step. For example, in the timing diagram 100 of FIG. 1, afirst signal tracel 10, is shown. First signal trace 110 represents theincoming reference clock signal REFCLK. The second signal trace 120represents the output of the coarse delay tuner circuit, and indicatesthat the first rising edge 130 occurs at a time equal to some fractionof the period T of the first signal trace 110, REFCLK. For illustrativepurposes, the fractional amount may be ¾, corresponding to the firstrising edge occurring at the time of 3T/4.

A coarse delay tuning circuit, for use in a DLL, includes a chain ofinverters which provide the required time delay. The required number ofinverters can be calculated with the following formula:total delay=delay per inverter (d)*number of inverters (n)In the instant case, the total desired delay is 3T/4, so 3T/4=d*n

Alternatively, number of inverters (n)=total delay/delay perinverter=3T/(4d). Typically, this number is on the order of a fewhundreds, and such a large number of inverters then additionallynecessitates the use of one or more decoders to dynamically select thenumber of inverters required at any moment.

Referring now to FIG. 2, an electrical schematic diagram of a coarsedelay tuner circuit in combination with an edge suppressor circuit inaccordance with an embodiment of the present invention is shown. Thecoarse delay tuner circuit 200 includes a low pass filter circuit 205, aSchmitt trigger circuit 210 and an edge suppressor circuit 250.

The low pass filter circuit 205 may be, inter alia, a first order R-Cnetwork, comprised of resistor 201 and capacitor 202, or it may be anyother suitable signal conditioning circuit suited to modifying the inputsignal to the required format. The input to the low pass filter circuit205 is the REFCLK signal which is the incoming reference clock signal.The REFCLK signal is integrated (i.e., a ramping signal is produced) bythe low pass filter circuit 205, resulting in a repeatedly rampingsignal at the input node IN. The ramping signal at input node IN is theinput to the Schmitt trigger circuit 210. In this illustrativeembodiment, Schmitt trigger circuit 210 is implemented withcomplementary metal-oxide-semiconductor (CMOS) transistors, namelyp-channel MOS (PMOS) transistors 211, 212, 215, and n-channel MOS (NMOS)transistors 213, 214, 216. Alternatively, Schmitt trigger circuit 210may be implemented with other combinations of MOSFET's, or with BJT's.Schmitt trigger circuit 210 produces an output signal at output node OP.This output signal is then directed to edge suppressor circuit 250. Dueto the inherent hysteresis operating characteristic found in Schmitttrigger circuits, the output signal at output node OP will remain in ahigh state until the input voltage at input node IN rises above a upperthreshold voltage for the particular transistors comprising the Schmitttrigger circuit 210. When the upper threshold voltage is exceeded, theoutput of the Schmitt trigger circuit 210 will switch to a low state.Conversely, the output signal at node OP will remain in a low stateuntil the input voltage at node IN drops below the lower thresholdvoltage to switch the output voltage at node OP to a high state.

Generally, Schmitt trigger circuit operation is known. Morespecifically, in an embodiment of the present invention, the Schmitttrigger circuit 210 receives a ramping signal via input node IN from thelow pass filter circuit 205. The ramping of the input signal at inputnode IN, after triggering by the Schmitt trigger circuit 210 atappropriate threshold levels, produces a string of output pulses fromthe Schmitt trigger circuit 210 at output node OP. Alternatively, theSchmitt trigger circuit 210 may be replaced by another suitabletriggering circuit, such as, inter alia, a Zener diode circuit.

The output pulses from output node OP are fed as the input to the edgesuppressor circuit 250, which comprises D-flipflops 260, 270, aninverter 280, and combinational means such as, inter alia, a pair oftwo-input NAND gates 290, 295. Edge suppressor circuit 250 may beconstructed using CMOS transistor technology, or other suitabletechnologies may be employed.

The D-flipflops 260, 270 are resettable, and positive edge triggered. Asis known, each D-flipflop comprises a data input (D), a clock input(CK), an output Q, and a reset or enable input (RST). Here, the power-onreset signal (POR) is used in resetting the output of the D flipflops260, 270 to zero. In operation, as the output pulse from the Schmitttrigger circuit 210 is passed to the edge suppressor circuit 250, apositive voltage step is produced at the output of NAND gate 290, atnode CL.

This positive step at node CL, when logically ANDed with the signal fromoutput node OP of the Schmitt trigger circuit 210, at NAND gate 295,produces the output clock signal OUTCLK. In this illustrative example,output signal OUTCLK has its first rising edge at time t=3T/4 of theoriginal incoming input REFCLK signal. Thus, the coarse delay tunercircuit 200 shifts the rising edge of the incoming clock signal REFCLKby 3T/4, or approximately 75% of the period T of the REFCLK signal. Thefunctionality of the coarse delay tuner circuit 200 can be furtherexplained via the timing diagram of FIG. 3. FIG. 3 is a timing diagramof the square wave, original input REFCLK signal 310, and the rampingsignal 320 at the node IN, which is the input to the coarse delay tunercircuit 200. Also shown are the Schmitt trigger circuit 210 outputsignal 330 at node OP, the positive step signal 340 at node CL of theedge suppressor circuit 250, and the output signal 350 at node OUTCLK.

As FIG. 3 shows, the output signal 350 of node OUTCLK has its firstrising edge at time t=3T/4 of the REFCLK signal, where T is the periodof the REFCLK signal. Embodiments of the present invention have beendisclosed. A person of ordinary skill in the art would realize, however,that certain modifications would come within the teachings of thisinvention. For example, rather than the particular transistor technologyrepresented by the embodiment discussed herein regarding FIG. 2, thepresent invention also encompasses embodiments incorporating othertransistor technologies. Similarly, inversions of the signals may beincluded. Therefore, the following claims should be studied to determinethe true scope and content of the invention.

1. A coarse delay tuner circuit for use with delay locked loops, said coarse delay tuner circuit comprising: an input node for receiving an input signal, wherein said input signal is a clock signal; a triggering circuit, said triggering circuit operationally coupled to said input node, wherein said triggering circuit conditions said input signal and to provides a first output signal in response to a threshold level being reached by said input signal; an edge suppressor circuit operationally coupled to said triggering circuit, wherein said edge suppressor circuit receives said first output signal, said edge suppressor circuit providinge a positive step signal as a second output signal, and wherein said edge suppressor circuit includes combinational means for logically combining said first output signal and said second output signal to produce a third output signal; and an output node for outputting said third output signal.
 2. The coarse delay tuner circuit of claim 1, further comprising a signal conditioning circuit operationally connected to said input node, said signal conditioning circuit preparing said input signal for use by said triggering circuit.
 3. The coarse delay tuner circuit of claim 2, wherein said signal conditioning circuit is a low pass filter circuit.
 4. The coarse delay tuner circuit of claim 3, wherein said low pass filter circuit is a first order R-C network.
 5. The coarse delay tuner circuit of claim 1, wherein said triggering circuit is a Schmitt trigger circuit.
 6. The coarse delay tuner circuit of claim 1, wherein said edge suppressor circuit further comprises: a first D-flipfiop, said first D-flipfiop having a clock input connected to said first output signal, a data input, a reset input connected to a power on reset signal, and an output connected to a first input of a first NAND gate; an inverter connected to said first output signal for producing an inverted input signal; a second D-flipflop, said second D-flipflop having a clock input connected to said inverted input signal, a data input connected to a power supply, a reset input connected to said power on reset signal, and an output connected to a second input of said first NAND gate, and to said data input of said first D-flip-flop; said first NAND gate having an output connected to a second input of a second NAND gate; and said second NAND gate having a first input connected to said first output signal, and said second NAND gate having an output for providing said third output signal.
 7. The coarse delay tuner circuit of claim 1, wherein said clock signal has a rising edge and a period, and said third output signal has a rising edge with a delay of about 75% of said period relative to the clock signal.
 8. A method for reducing lock time in a delay locked loop (DLL), said method comprising: providing an input node for receiving an input signal, wherein said input signal is a clock signal; providing a triggering circuit, said triggering circuit operationally coupled to said input node, wherein said triggering circuit conditions said input signal and provides a first output signal in response to a threshold level being reached by said input signal; providing an edge suppressor circuit operationally coupled to said triggering circuit, wherein said edge suppressor circuit receives said first output signal, said edge suppressor circuit providinge a positive step signal as a second output signal, and wherein said edge suppressor circuit includes combinational means for logically combining said first output signal and said second output signal to produce a third output signal; and providing an output node for outputting said third output signal.
 9. The method of claim 8, further comprising a signal conditioning circuit operationally connected to said input node, said signal conditioning circuit preparinge said input signal for use by said triggering circuit.
 10. The method of claim 9, wherein said signal conditioning circuit is a low pass filter circuit.
 11. The method of claim 10, wherein said low pass filter circuit is a first order R-C network.
 12. The method of claim 8, wherein said triggering circuit is a Schmitt trigger circuit.
 13. The method of claim 8, wherein said edge suppressor circuit further comprises: a first D-flipflop, said first D-flipflap having a clock input connected to said first output signal, a data input, a reset input connected to a power on reset signal, and an output connected to a first input of a first NAND gate; an inverter connected to said first output signal for producing an inverted input signal; a second D-flipflop, said second D-flipflop having a clock input connected to said inverted input signal, a data input connected to a power supply, a reset input connected to said power on reset signal, and an output connected to a second input of said first NAND gate, and to said data input of said first D-flip-flop; said first NAND gate having an output connected to a second input of a second NAND gate; and said second NAND gate having a first input connected to said first output signal, and said second NAND gate having an output for outputting said third output signal.
 14. The method of claim 8, wherein said clock signal has a rising edge and a period, and said third output signal has a rising edge with a delay of about 75% of said period relative to the clock signal. 